high speed parallel to serial converter ic

With the absence of pull-up resistors that are present in the case of I 2C, the power consumption of an SPI bus interface will be marginally lower than that of an I 2C interface. Bit-banging the SPI protocol using GPIO lines is also common, as is the case with I 2C. In SPI, sampling a data line and changing the data values must both be synchronized to the rising and falling edges of the clock line. The SPI protocol is comparable in complexity to the I 2C protocol-they are both quite simple. If there is a situation where both the master and slave need to transmit equal volumes of data to each other, this feature can be employed. This makes the SPI bus most suitable for sensors that produce a lot of data, such as, for example, fingerprint sensors.įull-duplex communication is enabled in the SPI protocol by default. Typical SPI bus speeds are in the 50 MHz range and with the absence of any protocol overhead as in the case of I 2C, this translates exactly into bit rate.

The key advantage of the SPI protocol is that it supports very high speeds, and by extension, throughput.

So, the effective throughput in the case mentioned can be as high as 100 Mbps (if both the master and slave are able to send meaningful data to each other). One more thing to remember is that the communication is full duplex. For a 50 MHz SPI line, the throughput is 50 Mbps. Since there is no overhead added by the protocol such as addressing and flow control, the throughput that can be achieved using SPI mirrors the clock frequency. Typical bus speeds are in the 50 MHz range. There is no standard set of speeds defined for the SPI protocol. The slave has no means of implementing/enforcing flow control and is expected to process all the data that it receives. The master controls the clock, so it can potentially use that to implement some form of flow control, but it is rarely done. There is no possibility for flow control in this protocol. In case either the master or the slave has no data to send, they can send 0 s. In each clock cycle, the master sends 1 bit to the slave, and the slave sends 1 bit to the master. The master then proceeds to operate the SCLK at a frequency less than or equal to the maximum frequency supported by the slave (typical speeds are in the MHz range). OperationĮach transaction begins with the master selecting a slave using the SS line. For a bus configuration where n slaves are connected to a master, (3 + n) pins will be required on the master. The SCLK, MOSI, and MISO lines are shared between all slaves. So, if n slaves are connected to a master in an SPI bus configuration, n SS pins are required on the master. The SS line is used by the master to select the slave that it wishes to communicate with.

High speed parallel to serial converter ic